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Proceedings of 2009 International Workshop on Information Security and Application (IWISA 2009)

Qingdao, China, November 21-22, 2009

Editors: Feng Gao and Xijun Zhu

AP Catalog Number: AP-PROC-CS-09CN004

ISBN: 978-952-5726-06-0

Page(s): 31-34

Design and Realization of Image Acquisition IP Core Based on Avalon Bus

Lushen Wu and Wenkai Ding

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The present study puts forward a new IP core design for real-time, high-speed image acquisition, based on Avalon bus. The proposed design can be described as follows. First, according to the top-down design philosophy, the IP core was functionally partitioned and hierarchically divided. Second, the IP core was driven and encapsulated under the HAL API. Third, the customized peripheral was added into Nios II system. The following experiment validated the low-power, high real-time of this IP core. Thus the customized image acquisition IP core based on Avalon bus was designed, realized and validated. Since IP core is configurable and can be well transplanted, it can be easily applied to embedded image acquisition system. And the IP core designed above has good portability and universal property.

Index Terms

FPGA, SOPC, Avalon bus, image acquisition, IP core

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