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Proceedings of the 2nd International Symposium on Information Processing (ISIP 2009)

Huangshan, China, August 21-23, 2009

Editors: Fei Yu, Jian Shu, and Guangxue Yue

AP Catalog Number: AP-PROC-CS-09CN002

ISBN: 978-952-5726-02-2 (Print), 978-952-5726-03-9 (CD-ROM)

Page(s): 179-183

A Clock Fault Detection Circuit for Nano-system by Time-to-Voltage Conversion

††††††† Changhong Yu

Full text:† PDF


With the high complexity and density of future nano-system, many aspects such as synchronization system control and system test will be difficult to manage. Clock signals will be suffer from low power supplying and high structural broking rate. As a result, clock fault become an inevitable problem in nano-circuits Self-detection and self-recovery for clock signal in systems are an important field of research in order to find solutions to these problems.

In this paper, we propose a novel compact and powerful architecture for clock fault detection in high speed nano-electronic system.† The totally new conception of time to voltage conversion is employed in our structure which can convert fault of time to the fault of voltage, which can be easily detected. The proposed circuit can work in very wide bandwidth and for different duty cycle by changing the charging and discharging capacitors. To illustrate the detection capability by the diction circuit, a prototype CMOS design of this proposed circuit is presented. Simulation result shows that the proposed architecture is very suit for integration to nano-electronic circuit design to detect the fault of the clock. These instructions give you basic guidelines for preparing camera-ready papers for APís conference proceedings.

Index Terms

nano-electronic, clock fault, fault tolerance, fault detection, nano-system

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