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Proceedings of 2009 International Symposium on Computer Science and Computational Technology (ISCSCT 2009)

Huangshan, China, December 26-28, 2009

Editors: Fei Yu, Guangxue Yue, Jian Shu, Yun Liu

AP Catalog Number: AP-PROC-CS-09CN005

ISBN: 978-952-5726-07-7 (Print), 978-952-5726-08-4 (CD-ROM)

Page(s): 102-105

A Kind of Low Complexity LDPC Decoder

Hang Jiang, Chun Xu, Qin Zhong, and Guifeng Zhong

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A kind of (1008, 3, 6) rules LDPC decoder was designed in this paper, in order to solving the high complexity of LDPC decoder hardware implementation, which adopted Min-Sum decoding algorithm and part-parallel structure. The minimum module in the traditional check function unit (CFU) was improved, which could reduce the complexity of the hardware realization. In the end, the LDPC decoder achieved the desired effect through the comparison of performance analysis, which laid a good foundation for the practical application.

Index Terms

LDPC, Min-Sum, part-parallel, minimum module, low complexity

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