ISSN : 1796-203X
Volume : 4    Issue : 10    Date : October 2009

Low Power Processor Architectures and Contemporary Techniques for Power Optimization – A Review
Muhammad Yasir Qadri, Hemal S. Gujarathi, and Klaus D. McDonald-Maier
Page(s): 927-942
Full Text:
PDF (828 KB)

The technological evolution has increased the number of transistors for a given die area significantly and
increased the switching speed from few MHz to GHz range. Such inversely proportional decline in size and
boost in performance consequently demands shrinking of supply voltage and effective power dissipation
in chips with millions of transistors. This has triggered substantial amount of research in power reduction
techniques into almost every aspect of the chip and particularly the processor cores contained in the chip.
This paper presents an overview of techniques for achieving the power efficiency mainly at the processor
core level but also visits related domains such as buses and memories. There are various processor
parameters and features such as supply voltage, clock frequency, cache and pipelining which can be
optimized to reduce the power consumption of the processor. This paper discusses various ways in which
these parameters can be optimized. Also, emerging power efficient processor architectures are
overviewed and research activities are discussed which should help reader identify how these factors in a
processor contribute to power consumption. Some of these concepts have been already established
whereas others are still active research areas.

Index Terms
Low power, processor architecture, power optimization techniques