JOURNAL OF COMPUTERS (JCP)
ISSN : 1796-203X
Volume : 4 Issue : 9 Date : September 2009
Modified CMOS Multiplication Algorithm Using Optimized Array Structure
Full Text: PDF (671 KB)
In this paper, a new, high-speed multiplication algorithm using tree circuit and a novel inner product
generator has been presented. In inner product generation step, a new Smith algorithm has been
modified. In inner product reduction step, a new array structure has been proposed. In final addition
step, a new algorithm has been used. In this work, improvements in multiplication algorithm by
using a faster counter along the tree are presented. In this paper, the novel presented multiplication
algorithm has been also analyzed in comparison with other multiplication algorithms. Based on the
variation of inner product generator methods, a novel Smith algorithm is proposed. This work,
presents a novel approach to reduce power of high-speed multiplication algorithm based on
decreasing number of inner products. The reducing elements used into the multiplication algorithm
architecture remove some inner product that have not effect in final addition. The proposed array
structure and Smith algorithm has major effect in multiplication algorithm performance. Previous
designs have been used to present a novel structure. A new multiplication algorithm is designed
and simulated in 80 nm process. We used SPICE and some programming code for simulations.
The latency has decreased by almost 15 percent and power consumption decreased by 14 percent.
Our design reduced transistor count by 10 percent.
CMOS, Counter, inner product, Smith algorithm, VLSI