JOURNAL OF COMPUTERS (JCP)
ISSN : 1796-203X
Volume : 4 Issue : 7 Date : July 2009
A High Density and Low Power Cache Based on Novel SRAM Cell
Arash Azizi Mazreah, Mohammad Taghi Manzuri, and Ali Mehrparvar
Full Text: PDF (1,744 KB)
Based on the observation that dynamic occurrence of zeros in the cache access stream and
cacheresident memory values of ordinary programs exhibit a strong bias towards zero, this paper
presents a novel CMOS five-transistor SRAM cell (5T SRAM cell) for very high density and low power
cache applications. This cell retains its data with leakage current and positive feedback without
refresh cycle. Novel 5T SRAM cell uses one word-line and one bit-line and extra read-line control.
The new cell size is 17% smaller than a conventional six-transistor SRAM cell using same design
rules with no performance degradation. Simulation and analytical results show purposed cell has
correct operation during read/write and also the average dynamic energy consumption of new cell is
30% smaller than a six-transistor SRAM cell.
5T SRAM cell, Read static noise margin free, Cell current, Cell leakage, Cell area, dynamic energy