ISSN : 1796-203X
Volume : 4    Issue : 6    Date : June 2009

Design Heuristics for Mapping Floating-Point Scientific Computational Kernels onto High Performance
Reconfigurable Computers
Justin L. Rice, Khalid H. Abed, and Gerald R. Morris
Page(s): 542-553
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Because of the increasing need to develop efficient high-speed computational kernels, researchers have
been looking at various acceleration technologies. One approach is to use field programmable gate
arrays (FPGAs) in conjunction with general purpose processors to form what are known as high
performance reconfigurable computers (HPRCs). HPRCs have already been shown to work well for both
fixed-point and integer calculations. Floating-point calculations are a different matter; obtaining speedups
has been somewhat elusive. This article, after introducing the three primary HPRC development flows,
takes a detailed look at “the three p’s,” which addresses the crucial relationship among performance,
pipelining, and parallelism. It also examines “the FPGA design boundary,” which addresses some of the
heuristics that allow developers to determine which application modules can be mapped onto the FPGAs.
These ideas are illustrated by way of a simple floating-point application that is mapped onto a
contemporary HPRC. This article expands upon earlier work by including details on how to map
customized intellectual property cores into an HPRC environment via a hybrid development flow.

Index Terms
high performance reconfigurable computer (HPRC), field programmable gate array (FPGA), algorithm