ISSN : 1796-203X
Volume : 4    Issue : 3    Date : March 2009

DL(2m): A New Scalable Interconnection Network for System-on-Chip
Youyao Liu, Jungang Han, and Huimin Du
Page(s): 201-207
Full Text:
PDF (190 KB)

With the feature size of semiconductor technology reducing and intellectual properties (IP) cores
increasing, on chip communication architectures have a great influence on the performance and
area of System-on-Chip(SoC) design. Network-on-Chip(NoC) has been proposed as a promising
solution to complex SoC communication problems and has been widely accepted by academe and
industry. Focusing on decreasing node degrees, reducing links and reusing router nodes, a regular
NoC architecture, named Double-Loop(DL(2m)) interconnection network, is proposed. The topology
of DL(2m) is simple, symmetric and scalable in architecture, and it is 3-regular plane graph with 4m
nodes. The nodes of DL(2m) adopt Johnson coding scheme that can make the design of routing
algorithms simple and efficient. The DL(2m) was compared with Ring and 2D Mesh by simulating
and analysing, both under uniform load and under more realistic load assumptions in the several
network size scenarios. The results show that the DL(2m) topology is a good trade-off between
performance and cost, and it is a better NoC topology when there are not too many network nodes.

Index Terms
system-on-chip, network-on-chip, network topology, routing algorithms