JOURNAL OF COMPUTERS (JCP)
ISSN : 1796-203X
Volume : 4    Issue : 2    Date : February 2009

Two New Low-Power and High-Performance Full Adders
Mohammad Hossein Moaiyeri, Reza Faghih Mirzaee, and Keivan Navi
Page(s): 119-126
Full Text:
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Abstract
Two new low-power, and high-performance 1-bit Full Adder cells are proposed in this paper. These
cells are based on low-power XOR/XNOR circuit and Majority-not gate. Majority-not gate, which
produces Cout (Output Carry), is implemented with an efficient method, using input capacitors and
a static CMOS inverter. This kind of implementation benefits from low power consumption, a high
degree of regularity and simplicity. Eight state-of-the-art 1-bit Full Adders and two proposed Full
Adders are simulated with HSPICE using 0.18µm CMOS technology at several supply voltages
ranging from 2.4v down to 0.8v. Although low power consumption is targeted in implementation of
our designs, simulation results demonstrate great improvement in terms of power consumption
and also PDP.

Index Terms
Full Adder Cell, Majority-not Gate, Low-Power, High-Performance, Power-Delay Product