JOURNAL OF COMPUTERS (JCP)
ISSN : 1796-203X
Volume : 3    Issue : 5    Date : May 2008

Low Power SRAM with Boost Driver Generating Pulsed Word Line Voltage for Sub-1V Operation
Masaaki Iijima, Kayoko Seto, Masahiro Numa, Akira Tada, and Takashi Ipposhi
Page(s): 34-40
Full Text:
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Abstract
Instability of SRAM memory cells derived from the process variation and lowered supply voltage has
recently been posing significant design challenges for low power SoCs. This paper presents a
boosted word line voltage scheme, where an active bodybiasing controlled boost transistor
generates a pulsed word line voltage by capacitive coupling only when accessed. Simulation
results have shown that the proposed approach not only shortens the access time but mitigates the
impact of Vth variation on performance even at ultra low supply voltage less than 0.5 V.

Index Terms
SRAM, Circuit methodology, Low power, Low voltage, PD-SOI, Vth variation