ISSN : 1796-203X
Volume : 3    Issue : 4    Date : April 2008

Leakage Controlled Read Stable Static Random Access Memories
Sayeed A. Badrudduza, Ziyan Wang, Giby Samson, and Lawrence T. Clark
Page(s): 39-49
Full Text:
PDF (660 KB)

Semiconductor manufacturing process scaling increases leakage and transistor variations, both of
which are problematic for static random access memory (SRAM). Since SRAM is a critical
component in modern CMOS integrated circuits, novel approaches to addressing these problems
are needed. Here, six and seven transistor SRAM cells are presented that do not suffer from
reduced stability when read. The cells reside in a low leakage, voltage collapsed, low standby
power mode when not being accessed. Both six transistor and seven transistor variations of the
basic approach are explored through simulation and measured results. The circuit topology, layout,
and impact on memory design of the proposed cell designs are described. Measured results on a
130 nm foundry fabrication process demonstrate the viability of three of the possible cell
configurations. Circuit simulation is used to explore the cell stability in the presence of process
variations, and to show the value of the proposed SRAM cell designs on future scaled
manufacturing technologies.

Index Terms
SRAM, static noise margin, reverse body bias, leakage reduction