ISSN : 1796-203X
Volume : 3    Issue : 4    Date : April 2008

Thermal Driven Placement for Island-style MTCMOS FPGAs
Javid Jaffari and Mohab Anis
Page(s): 24-30
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Rapid increase in transistor density and operating frequency has led to the increase in power
densities, exhibiting itself as a high temperature profile. The high temperature spots over an FPGA
impact the power, performance, and reliability of the chip, hence should be addressed during the
design process. The logic block placement is targeted as the natural starting point to address the
non-uniform thermal profile problem. The proposed placer simultaneously accounts for
conventional placement objectives (routability and timing) while increases the temperature profile
uniformity by optimizally spreading the power sources. As a measure of thermal uniformity in the
simulation annealing core of the placer, a cost function is derived by adapting the concept of
maximum entropy in a dual electrostatic charge model. The runtime complexity of this cost function
is linear with respect to the number of used blocks, regardless of the size of the FPGA, and there is
no need to perform the time-consuming thermal extractions. Results show an average of 73% and
51% reductions in the standard deviation and maximum gradient of temperature with less than 4%
average wiring and delay penalty.

Index Terms
FPGA, Placement, Temperature, Maximum Entropy, Simulation Annealing