JOURNAL OF COMPUTERS (JCP)
ISSN : 1796-203X
Volume : 3 Issue : 4 Date : April 2008
Practical Chip-level Equalizers in HSDPA
Minjae Park, Woonsik Lee, Minh-Viet Nguyen, and Hwang Soo Lee
Full Text: PDF (1,229 KB)
High-speed downlink packet access (HSDPA) has been developed to upgrade the current WCDMA
system in yerms of providing a higher data rate for mobile users. To ensure a downlink speed of up
to 14Mbps, the HSDPA system has three main features: adaptive modulation and coding, a hybrid
automatic repeat request, and fast scheduling. Because standard documents describe only the
specifications of Node B, various kinds of HSDPA receivers cen be used with different architectures.
An ordinary receiver generally has a rake architecture, though a rake receiver is not good at reducing
multiple access interference (MAI). The performance of rake receiver is indispensably deteriorated
when the number of mobile users in the system increases. Conversely, an equalizer can alleviate
the MAI significantly at the expense of complexity and can therefore be an alternative solution for a
rake receiver in a HSDPA system. In this paper, the performance of several equalizers of a HSDPA
system is compared in terms of several implementation issues. The simulation results provide
useful information about proper equalizers for different design purposes with respect to the
performance and complexity trade-off.
WCDMA, HSDPA, equalizer.