JOURNAL OF COMPUTERS (JCP)
ISSN : 1796-203X
Volume : 3    Issue : 3    Date : March 2008

Performance Comparisons, Design, and Implementation of RC5 Symmetric Encryption Core
using Reconfigurable Hardware
Omar Elkeelany and Adegoke Olabisi
Page(s): 48-55
Full Text:
PDF (539 KB)


Abstract
With the wireless communications coming to homes and offices, the need to have secure data
transmission is of utmost importance. Today, it is important that information is sent confidentially
over the network without fear of hackers or unauthorized access to it. This makes security
implementation in networks a crucial demand. Symmetric Encryption Cores provide data protection
via the use of secret key only known to the encryption and decryption ends of the communication
path. In this paper, first, an overview of two well known symmetric encryption cores is presented,
namely the 3DES and RC5. Then a performance evaluation of their computer based
implementation is compared to demonstrate the RC5 superior performance. The conventional
hardware architecture of the RC5 core is presented and investigated. A hardware system design is
proposed to improve its performance. The proposed architecture achieved with three stage pipeline
technique an increased encryption throughput as compared to related work. By exploiting modern
features in Field Programmable Gate Arrays (FPGA), which allow the modeling of a Systemon-
Programmable-Chip (SoPC), this paper proposes a model for symmetric encryption algorithms (    
e.g., RC5). Structural System analysis of the proposed model shows that it offers extra security
against single-site physical access attack that other implementations are vulnerable to. By
evaluating the performance of this proposed SoPC model, one finds that it raises the encryption
throughput to 300 Mbps. Hence, we report over 80% increase in the encryption throughput as
compared to related work. Moreover, our work lowers the implementation cost due to the integration
of all system parts into one chip.

Index Terms
Cryptography, Systems-on-Programmable Chips, analysis and simulation, Hardware Description
Language