JOURNAL OF COMPUTERS (JCP)
ISSN : 1796-203X
Volume : 3    Issue : 3    Date : March 2008

Comparative Study on Leakage Current of Power-Gated SRAMs for 65-nm, 45-nm, and 32-nm
Technology Nodes
Duk-Hyung Lee, Dong-Kone Kwak, and Kyeong-Sik Min
Page(s): 39-47
Full Text:
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Abstract
In this paper, we compare four SRAM circuits. They are the conventional SRAM1, the SRAM2 with
power switches on VSS line, the SRAM3 with switches on VDD line, and the SRAM4 with switches
on both VDD and VSS lines, respectively. Among the four SRAMs, the SRAM2 shows the smallest
amount of leakage, because its subthreshold leakage is most suppressed by its BODY and
Drain-Induced Barrier Lowering (DIBL) effects. In addition, the area overheads of the SRAM2,
SRAM3, and SRAM4 are also compared thus the SRAM2 being found most favorable in terms of the
area penalty. To reduce the oxide-tunneling leakage more, the SRAM5 with precharge voltage
lowering is considered in this paper. Compared with the SRAM2 without lowering the precharge
voltage, amounts of leakage of the SRAM5 are suppressed by 24.4%, 13.1%, and 4.2%,
respectively, at -25°C, 25°C, and 100°C, for the 65-nm node.

Index Terms
Oxide-tunneling leakage, Sub-threshold leakage, Low-leakage, SRAM, Memory