JOURNAL OF COMPUTERS (JCP)
ISSN : 1796-203X
Volume : 3    Issue : 3    Date : March 2008

Power-efficient Instruction Encoding Optimization for Various Architecture Classes
Diandian Zhang, Anupam Chattopadhyay, David Kammler, Ernst Martin Witte, Gerd Ascheid, Rainer
Leupers, and Heinrich Meyr
Page(s): 25-38
Full Text:
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Abstract
A huge application domain, in particular, wireless and handheld devices strongly requires flexible
and power-efficient hardware with high performance. This can only be achieved with Application
Specific Instruction-Set Processors (ASIPs). A key problem is to determine the instruction encoding
of the processors for achieving minimum power consumption in the instruction bus and in the
instruction memory. In this paper, a framework for determining power-efficient instruction encoding
in RISC and VLIW architectures is presented. We have integrated existing and novel techniques in
this framework and propose novel heuristic approaches. The framework accepts an existing
processor’s instruction-set and a set of implementations of various applications. The output, which
is an optimized instruction encoding under the constraint of a well-defined cost model, minimizes
the power consumption of the instruction bus and the instruction memory. This results in strong
reduction of the overall power consumption. Case studies with commercial embedded processors
show the effectiveness of this framework.

Index Terms
power-efficient, instruction encoding, instruction memory, instruction bus, embedded processors