JOURNAL OF COMPUTERS (JCP)
ISSN : 1796-203X
Volume : 3 Issue : 3 Date : March 2008
Simultaneous Sleep Transistor Insertion and Power Network Synthesis for Industrial Power
Kaijian Shi, Zhian Lin, Yi-Min Jiang, and Lin Yuan
Full Text: PDF (539 KB)
Sleep transistors in industrial power-gating designs are custom designed with an optimal size.
Consequently, sleep transistor P/G network optimization becomes a problem of finding the optimal
number of sleep transistors and their placement as well as optimal P/G network grids, wire widths
and layers. This paper presents a fake via based sleep transistor P/G network synthesis method,
which addresses the requirements from industrial power-gating designs. The method produces
optimal sleep transistor P/G networks by simultaneously optimizing sleep transistor insertion and
placement as well as the power network grids and wires for minimum area, maximum routability
with a given IR-drop target.
power-gating, sleep transistor, switch cell, P/G network synthesis, method, algorithm, low power