JOURNAL OF COMPUTERS (JCP)
ISSN : 1796-203X
Volume : 3    Issue : 2    Date : February 2008

Low-Power and High-Performance 1-Bit CMOS Full-Adder Cell
Keivan Navi, Omid Kavehei, Mahnoush Rouholamini, Amir Sahafi, Shima Mehrabi, and Nooshin
Dadkhahi
Page(s): 48-54
Full Text:
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Abstract
In this paper a new low power and high performance adder cell using a new design style called
“Bridge” is proposed. The bridge design style enjoys a high degree of regularity, higher density than
conventional CMOS design style as well as lower power consumption, by using some transistors,
named bridge transistors. Simulation results illustrate the superiority of the resulting proposed
adder against conventional CMOS 1-bit full-adder in terms of power, delay and PDP. We have
performed simulations using HSPICE in a 90 nanometer (nm) standard CMOS technology at room
temperature; with supply voltage variation from 0.65v to 1.5v with 0.05v steps.

Index Terms
CMOS Circuit, VLSI, Full adder, Bridge style