JOURNAL OF COMPUTERS (JCP)
ISSN : 1796-203X
Volume : 3    Issue : 2    Date : February 2008

Process Variation Aware Transistor Sizing for Load Balance of Multiple Paths in Dynamic CMOS
for Timing Optimization
Kumar Yelamarthi and Chien-In Henry Chen
Page(s): 21-28
Full Text:
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Abstract
The complexity in timing optimization of highperformance microprocessors has been increasing
with the number of channel-connected transistors in various paths of dynamic CMOS circuits and
the rising magnitude of process variations in nanometer CMOS process. In this paper, a process
variation aware transistor sizing algorithm for dynamic CMOS circuits while considering the Load
Balance of Multiple Paths (LBMP) is proposed. The proposed iterative optimization algorithm is a
deterministic approach and is illustrated first by a 2-b weighted binary-tothermometric converter
(WBTC) and of which the critical path was optimized from an initial delay of 355 ps to an optimal
delay of 157 ps, which accounts for a 55.77% delay improvement. A 4-b unity weight
binary-to-thermometric converter (UWBTC) was also designed and of which the critical path was
optimized from an initial delay of 152 ps to an optimal delay of 103 ps, which accounts for a 32.23%
delay improvement. Finally, a 64-b parallel binary adder was partitioned to a mixed dynamic-static
CMOS style and the critical path and the power delay product were optimized to 632 ps and 84.17 pJ
respectively.

Index Terms
dynamic CMOS logic, transistor sizing, timing optimization, process variations,
binary-tothermometer decoder, parallel binary adders.