ISSN : 1796-203X
Volume : 1    Issue : 1    Date : April 2006

Hardening FPGA-based Systems Against SEUs: A New Design Methodology
L. Sterpone and M. Violante
Page(s): 22-30
Full Text:
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SRAM-based Field Programmable Gate Arrays (FPGAs) are very susceptible to Single Event Upsets
(SEUs) that may have dramatic effects on the circuits they implement. In this paper we present a
design flow composed by both standard tools, and ad-hoc developed tools, which designers can
use fruitfully for developing circuits resilient to SEUs. Experiments are reported on both benchmarks
circuits and on a realistic circuit to show the capabilities of the proposed design flow.

Index Terms
FPGA, SEU, fault tolerance