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International Journal of

Recent Trends in Engineering

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International Journal of Recent Trends in Engineering (IJRTE)

ISSN 1797-9617

Volume 1, Number 4, May 2009

Issue on Electrical & Electronics

Page(s): 29-31

Power and Delay Analysis of a 2-to-1 Multiplexer Implemented in Multiple Logic Styles for Multiplexer-Based Decoder in Flash ADC

Ms.G.L.Madhumati, M.Madhavilatha, and Mr.K.Ramakoteswara Rao

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Abstract

Thermometer - to - Binary decoders has become bottleneck in the ultra-high speed flash ADCs. Among various types of decoders available multiplexer-based decoder requires less hardware, has more regular structure and shorter critical path. A 2-to-1 multiplexer is the leaf cell in the decoder. In this paper the authors have analyzed a 2-to-1 multiplexer circuit using complementary CMOS, dynamic and pass-transistor logic styles. The power consumption, delay, area and power-delay product of various logic styles are compared. This paper shows that 2T multiplexer is an optimum device level design which has characteristics of high speed with minimum power compared with other realizations.

Index Terms

Thermometer code, Flash ADC, CPL, EEPL, LEAP.

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