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International Journal of

Recent Trends in Engineering

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International Journal of Recent Trends in Engineering (IJRTE)

ISSN 1797-9617

Volume 1, Number 3, May 2009

Issue on Electrical & Electronics

Page(s): 311-315

VLSI Implementation of the Fourphase Pulse Compression Sequences

N. Balaji, K. Subba Rao and M. Srinivasa Rao

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Fourphase codes have been widely used in radar and communication areas, but the synthesis of Fourphase codes with good merit factor is a nonlinear multivariable optimization problem, which is usually difficult to tackle. To get the solution of above problem many global optimization algorithms like genetic algorithm, simulated annealing, and tunneling algorithm were reported in the literature. However, there is no guarantee to get global optimum point. In this paper, a novel and efficient VLSI architecture is proposed to design Fourphase Pulse compression sequences with good Merit factor. The VLSI architecture is implemented on the Field Programmable Gate Array (FPGA) as it provides the flexibility of reconfigurability and reprogramability. The implemented architecture overcomes the drawbacks of non guaranteed convergence of the earlier optimization algorithms.

Index Terms

Pulse compression, Binary sequence, VLSI architecture, Merit Factor, Sidelobe energy, FPGA

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