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International Journal of

Recent Trends in Engineering

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International Journal of Recent Trends in Engineering (IJRTE)

ISSN 1797-9617

Volume 1, Number 1, May 2009

Issue on Computer Science

Page(s): 393-397

Design Space Exploration of Mesh Based Network-on-Chip Architectures

Rabindra K Jena, S. Pattnaik

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Design space exploration and performance evaluation are the most essential task in NoC design. In this paper, we proposed a design space exploration framework using analytical modeling. We have considered many-many mapping between cores and switches. A buffer allocation algorithm for wormhole routing based networks-on-chip is proposed for the design space exploration. When the total budget of the available buffering space is fixed, the proposed algorithm automatically assigns the buffer depth for each input channel, in different routers across the chip based on traffic characteristics of the target application.

Index Terms

NoC, Analytical Model, Design Space Exploration

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