Home††††††† Author Index††††††† Search†††††††††††††††† Volume 1††††† May 2009††††† ISSN 1797-9617

International Journal of

Recent Trends in Engineering

Home > Vol. 1, No. 1

 

International Journal of Recent Trends in Engineering (IJRTE)

ISSN 1797-9617

Volume 1,† Number 1,† May 2009

Issue on Computer Science

Page(s): 168-172

Robust Verification of Public Marks in FPGA Design through a Zero-Knowledge Protocol

†††††††††† Debasri Saha and Susmita Sur-Kolay

Full text:† PDF

Abstract

With more integration in VLSI technology, Intellectual Property (IP) cores are reused to meet the customerís specifications in time. For intellectual property protection (IPP), various kinds of IP marks, such as watermarks, fingerprints, are embedded into the design for establishing the veracity of a legal IP owner. However, convincing public verification of such marks is not leakage-proof. Attackers not only manage to obtain potential clues to tamper public marks rendering public verification invalid, but can also suitably override the marks to include own signature, resulting in wrong public identification of IP vendor and IP buyer. Furthermore, current technique includes a sufficiently large set of public marks containing a header and a message body in addition to private ones to facilitate only public verification at the cost of significant increase in design overhead. We propose a zero-knowledge protocol to ensure robust and leakage proof convincing public verification with a smaller set of public marks consisting of only header part. We have tested our protocol for FPGA benchmarks and the results on robustness and overhead are encouraging.

Index Terms

FPGA design, intellectual property protection, mark verification, zero-knowledge protocol.

Published by Academy Publisher in cooperation with the ACEEE

@ Copyright 2009 ACADEMY PUBLISHER ó All rights reserved